1. Field of Invention
This invention relates to integrated circuits and, more particularly, to the testing of a circuit for signal skewing at the output of the circuit using a relatively low impedance test characterization load.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Integrated circuits manufactured today generally have thousands of active and passive devices interconnected on a single monolithic substrate. Advances in design and manufacturing techniques provide even greater levels of integration, whereby multiple subsystems can be arranged on a single substrate. Each system performs a specified function and ideally presents an output at an expected time.
To ensure the proper operation of each system upon an integrated circuit, the integrated circuit is generally tested as part of a debug operation, either as the integrated circuit is being designed or after it has been designed and is in production. Data collected from the test operation may be used to improve performance or enhance yield. The basis for testing of complex integrated circuits is to isolate a particular circuit subsystem portion of the integrated circuit, and test that portion. The portion of the integrated circuit that receives test stimuli can be referred to as a device under test or “DUT.” The terms DUT and integrated circuit portion, or simply circuit, are henceforth used interchangeably.
A typical test operation involves applying the input stimuli or test vector to the DUT, and reading a response at the DUT output. A comparison is then made of an expected DUT output to the actual DUT output on a cycle-by-cycle basis. If the output signal and the expected output signal are not in agreement, the DUT is usually considered defective.
There are numerous mechanisms used to apply test vectors, read output signals, and compare the output signals to expected output signals. For example, the integrated circuit may contain its own logic built into the monolithic substrate, often referred to as a built-in-self-test (BIST). The BIST circuitry applies the vector and reads the response without the use of an external tester. Another technique is generally referred to as the scan test technique, wherein data for testing is shifted into the DUT and the results are read and thereafter compared against the expected results. Instead of BIST, external testers can be used to supply the stimuli and read the response via, for example, input and output pins on the integrated circuit.
Multiplexers can be used to select the pins as being either in a test mode or a normal mode of operation. For example, a multiplexer on an input pin can be selected to receive a test vector, and a multiplexer on an output pin can be selected to present the test result. If the multiplexers are not selected in a test mode, then the input pins can be used to receive, for example, an address and the output pins can be used to send corresponding data.
Regardless of the test technique chosen, a test operation typically involves two types of tests: a functionality test and a timing (or characterization) test. Functionality testing might simply be writing a test pattern of 1s and 0s into the DUT and reading the logic values from the DUT. Hopefully, the pattern read from the DUT will match the pattern written to the DUT. Functionality testing thereby simply involves checking whether the output signal logic value matches the expected output signal. Consideration is not given to whether the output signal arrives at a particular time and, thus, timing testing or characterization testing is often needed in addition to functional testing.
Characterization testing generally involves checking that the output of the DUT occurs at a proper, specified time. Typical characterization tests include tests to determine the output signal transitions relative to clock transitions, propagation delays, set-up and hold times, access times, minimum and maximum speed of operation, rise and fall time, and others. These tests are captured in timing characterizations and used in a test system to verify performance of the device. The various comparisons of when signals appear relative to when the signal is expected to appear is henceforth referred to as signal skew. Thus, comparing a signal occurring at a particular time to when that signal is expected to occur is hereby referred to, generally, as characterization testing or simply testing or measuring for signal skew.
It would be desirable to perform both functional and characterization testing on separate circuits (DUTs) within an overall integrated circuit. It would also be desirable to place the circuits used for performing characterization testing upon the integrated circuit. The characterization testing thereby forms a characterization path. It would also be desirable to carefully implement the characterization path into a functional path so that the DUT output does not experience undue loading of any signal placed on that output. If the loading is properly minimized, then any output signal arising from a test pattern will arrive on the tester without undue delay. Moreover, during normal operations, the characterization path will not slow the ramp times on the output pin of the integrated circuit and, during test times, will not induce inaccuracies into the characterization result.